Currently, I/O devices not only do simple functions such as changing data formats, but are also operated under control of a preprogram. Therefore, a register conflict may occur whenever both the I/O device and a central processing unit (hereinafter referred to as a CPU) simultaneously access the same register. For example, when a write operation to a register which may be included in the I/O device is executed under control of the preprogram controlling the I/O device, the CPU of the microcomputer may also access the register to write new data. Then, the content of the register will not be specified by both the I/O devices and the CPU because of the interference between the two write operations to the register.
In a conventional system, for example, as in Japanese Patent Laid-Open Sho 54-58117 disclosure, the operation of the CPU is given a priority over that of the I/O device in accessing a register which is commonly addressable by both the CPU and the I/O device. Namely, when the write operation to the register by both the CPU and the I/O device occurs, the operation by the I/O device will be ineffective. This means that although a register conflict is prevented, the performance of the I/O device is undesirably delayed.